1) Field of the Invention
This invention relates to a data processing apparatus having a coprocessor for asynchronously processing commands to execute commands at a high speed, an exception processing method for processing, when an exception occurs at a coprocessor, the exception, and a method of verifying the regularity of operation of the coprocessor.
2) Description of the Prior Art
In order to process an exception precisely with a data processing apparatus having a coprocessor such as, for example, a floating-point calculation apparatus, information of the exception must be reported in detail as the need arises. Further, in order to verify whether an operation dependent upon occurrence of an exception is performed correctly, an abnormal condition must be set in the program and a result of the abnormal condition must be confirmed.
An exemplary one of conventional exception processing systems for an asynchronous coprocessor is disclosed, for example, in Japanese Patent Laid-Open Application No. Heisei 4-106652. In the conventional exception processing system, only direct information regarding a coprocessor command with which an exception has occurred is notified to a central processing unit (hereinafter CPU) from a coprocessor. Here, an exception signifies an event wherein a command cannot be executed regularly, for example, a certain value is divided by 0 or an inaccessible area is designated by an operand in a command.
FIG. 6 schematically shows an exemplary construction of a data processing apparatus of the type described above. Referring to FIG. 6, the data processing apparatus shown includes a CPU 60 for executing a command, and a coprocessor 70 connected to the CPU 60 for asynchronously executing coprocessor commands issued by the CPU 60.
A memory 64 is provided for the CPU 60. The CPU 60 includes a command control section 61, a plurality of general-purpose registers 62 and an arithmetic unit 63. The coprocessor 70 includes a control section 71, at least one coprocessor arithmetic unit 72 and a coprocessor command queue 73.
A coprocessor command bus 81 is provided between the command control section 61 and the coprocessor command queue 73 for transmitting coprocessor commands from the command control section 61 to the coprocessor command queue 73. A register number bus 82 is provided between the control section 71 and the general-purpose registers 62 for transmitting write register numbers, read register numbers, and so forth, from the control section 71 to the general-purpose registers 62.
A source data bus 83 is provided between the general-purpose registers 62 and the data input side of the coprocessor arithmetic unit 72 for transmitting source data from the general-purpose registers 62 to the coprocessor arithmetic unit 72. An output bus 84 is provided between the calculation result output side of the coprocessor arithmetic unit 72 and the general-purpose registers 62 for transmitting the output of the coprocessor arithmetic unit 72 to the general-purpose registers 62.
The command control section 61 of the CPU 60 synchronously and successively reads out program commands stored in the memory 64 and sequentially executes the program commands. The command control section 61 notifies commands to the coprocessor 70 by way of the coprocessor command bus 81 when commands to be calculated by the coprocessor 70 are detected during execution of the series of commands.
The control section 71 of the coprocessor 70 controls a calculation processing operation of the coprocessor arithmetic unit 72 and controls and executes an exception processing operation, hereinafter described, when an exception occurs during calculation processing of the coprocessor arithmetic unit 72.
The coprocessor arithmetic unit 72 of the coprocessor 70 receives source data from the general-purpose registers 62 of the CPU 60, executes calculation processing using the source data in response to an instruction from the control section 71 and outputs a result of the calculation to the general-purpose registers 62 of the CPU 60.
In this instance, source data are inputted, to the coprocessor arithmetic unit 72 from that one of the general-purpose registers 62 which has a read register number designated by the control section 71, or where a plurality of coprocessor arithmetic units 72 are provided, to a selected one of the coprocessor arithmetic units 72, by way of the source data bus 83. Meanwhile, the result of calculation by the coprocessor arithmetic unit 72 is written, via the register number bus 82 by way of the output bus 84, into the general-purpose register 62 which has a write register number designated by the control section 71.
The coprocessor command queue 73 of the coprocessor 70 stores coprocessor commands notified thereto from the command control section 61 of the CPU 60 by way of the coprocessor command bus 81. The coprocessor command queue 73 includes a plurality of exception flag registers 74 each for storing, when an exception has occurred in the coprocessor 70, a flag representing the occurrence of an exception.
In the data processing apparatus constructed in such a manner as described above, when an exception occurs during calculation processing in the coprocessor arithmetic unit 72, a type of the exception is written into a corresponding one of the exception flag registers 74 provided in the coprocessor command queue 73.
Meanwhile, the control section 71 recognizes an exception occurrence position at the coprocessor command queue 73, discriminates a type of the exception from the exception flag register 74 and executes exception processing in accordance with the type of the exception. Then, the control section 71 notifies the CPU 60 of information regarding the coprocessor command at which the exception has occurred.
In the conventional data processing apparatus described above, information other than information regarding a coprocessor command at which an exception has occurred except that a result of calculation is reported from the coprocessor arithmetic unit 72 to the CPU 60. Accordingly, the CPU 60 cannot readily grasp a flow of processing in the coprocessor 70 executed under a series of commands at a point of time at which an exception occurs. Consequently, the conventional data processing apparatus has a problem in that the CPU 60 cannot make a suitable determination of a cause of occurrence of an exception which has occurred in the coprocessor 70 and the CPU 60 cannot execute processing based on an appropriate determination regarding the exception.
Further, in the conventional data processing apparatus, access from the CPU 60 to the coprocessor command queue 73 is permitted to write a coprocessor information, but any other access from the CPU 60 to the coprocessor command queue 73 is not permitted. Accordingly, the conventional data processing apparatus has another problem in that it is difficult for the CPU 60 to verify whether coprocessor commands instructed from the CPU 60 to the coprocessor 70 are held regularly in the coprocessor command queue 73 and also in that, when the processing of the CPU 60 returns to regular processing, the CPU 60 cannot change the information in the coprocessor command queue 73 arbitrarily and consequently the CPU 60 cannot take a flexible countermeasure against an exception.